
`timescale 1ns/1ps

module LCD_Driver #(parameter 		IMAGE_X = 2200,
												IMAGE_Y = 1125,
												H_FRONT = 88,
												H_BACK 	= 148,
												HSYNC_L = 44,
												V_FRONT = 4,
												V_BACK 	= 36,
												VSYNC_L = 5,
												
												DATAWIDTH = 8,
												OUTPUT_REG = 0
												)
								(
	input 									clk,
	input 									rst_n,
	
	input[DATAWIDTH-1:0] 				Rin,
	input[DATAWIDTH-1:0] 				Gin,
	input[DATAWIDTH-1:0] 				Bin,
	
	output reg 								data_req,
	output reg 								vsync,
	output reg 								hsync,
	output reg 								de,
	output reg[DATAWIDTH-1:0] 			Rout,
	output reg[DATAWIDTH-1:0] 			Gout,
	output reg[DATAWIDTH-1:0] 			Bout
	);
	
//parameter IMAGE_X = 1056,
//			 IMAGE_Y = 628,
//			 H_FRONT = 40,
//			 H_BACK 	= 88,
//			 HSYNC_L = 128,
//			 V_FRONT = 1,
//			 V_BACK 	= 23,
//			 VSYNC_L = 4;
			 
reg[12:0] hcnt;
reg[12:0] vcnt;


always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
	hcnt <= 13'd0;
else if(hcnt==IMAGE_X-1)
	hcnt <= 13'd0;
else
	hcnt <= hcnt + 13'd1;
end

always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
	vcnt <= 12'd0;
else if(hcnt==IMAGE_X-1)
	begin
	if(vcnt==IMAGE_Y-1)
		vcnt <= 12'd0;
	else
		vcnt <= vcnt + 12'd1;
	end
end

always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
	hsync <= 1'b0;
else if(hcnt<HSYNC_L+H_BACK)
	hsync <= 1'b1;
else
	hsync <= 1'b0;
end

always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
	vsync <= 1'b0;
else if(hcnt==0)
	begin
	if((vcnt>=0) && (vcnt< VSYNC_L))
		vsync <= 1'b1;
	else
		vsync <= 1'b0;
	end
end


always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
	de <= 1'b0;
else if((vcnt<V_BACK+VSYNC_L)||(vcnt>IMAGE_Y-V_FRONT-1))
	de <= 1'b0;
else if((hcnt>H_BACK+HSYNC_L-5)&&(hcnt<IMAGE_X-H_FRONT-4))
	de <= 1'b1;
else
	de <= 1'b0;
end

always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
	data_req <= 1'b0;
else if((vcnt<V_BACK+VSYNC_L)||(vcnt>IMAGE_Y-V_FRONT-1))
	data_req <= 1'b0;
else if((hcnt>H_BACK-6+HSYNC_L)&& (hcnt<IMAGE_X-H_FRONT-5))
	data_req <= 1'b1;
else 
	data_req <= 1'b0;
end

always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
	Rout <= 10'd0;
else
	Rout <= Rin;
end

always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
	Gout <= 10'd0;
else
	Gout <= Gin;
end

always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
	Bout <= 10'd0;
else 
	Bout <= Bin;
end

endmodule

	
	
	